// 编写一个模块，实现循环输出序列001011。
module sequence_generator(
           input clk,
           input rst_n,
           output reg data
       );
reg [2: 0] cnt;
always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			cnt <= 3'd0;
		else if (cnt == 3'd5)
			cnt <= 3'd0;
		else
			cnt <= cnt + 1'b1;
	end

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			data <= 1'b0;
		else if (cnt == 3'd2 | cnt == 3'd4 | cnt == 3'd5)
			data <= 1'b1;
		else
			data <= 1'b0;
	end
endmodule
